1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method of controlling stepper process parameters based upon optical properties of incoming process layers, and a system for accomplishing same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
By way of background, an illustrative field effect transistor 10, as shown in FIG. 1, may be formed above a surface 15 of a semiconducting substrate or wafer 11 comprised of doped-silicon. The substrate 11 may be doped with either N-type or P-type dopant materials. The transistor 10 may have a doped polycrystalline silicon (polysilicon) gate electrode 14 formed above a gate insulation layer 16. The gate electrode 14 and the gate insulation layer 16 may be separated from doped source/drain regions 22 of the transistor 10 by a dielectric sidewall spacer 20. The source/drain regions 22 for the transistor 10 may be formed by performing one or more ion implantation processes to introduce dopant atoms, e.g., arsenic or phosphorous for NMOS devices, boron for PMOS devices, into the substrate 11. Shallow trench isolation regions 18 may be provided to isolate the transistor 10 electrically from neighboring semiconductor devices, such as other transistors (not shown).
The gate electrode 14 has a critical dimension 12, i.e., the width of the gate electrode 14, that approximately corresponds to the channel length 13 of the device when the transistor 10 is operational. Of course, the critical dimension 12 of the gate electrode 14 is but one example of a feature that must be formed very accurately in modern semiconductor manufacturing operations. Other examples include, but are not limited to, conductive lines, openings in insulating layers to allow subsequent formation of a conductive interconnection, i.e., a conductive line or contact, therein, etc.
In the process of forming integrated circuit devices, millions of transistors, such as the illustrative transistor 10 depicted in FIG. 1, are formed above a semiconducting substrate. In general, semiconductor manufacturing operations involve, among other things, the formation of layers of various materials, e.g., polysilicon, insulating materials, etc., and the selective removal of portions of those layers by performing known photolithographic and etching techniques. These processes are continued until such time as the integrated circuit device is complete. Additionally, although not depicted in FIG. 1, a typical integrated circuit device is comprised of a plurality of conductive interconnections, such as conductive lines and conductive contacts or vias, positioned in multiple layers of insulating material formed above the substrate. These conductive interconnections allow electrical signals to propagate between the transistors formed above the substrate.
During the course of fabricating such integrated circuit devices, a variety of features, e.g., gate electrodes, conductive lines, openings in layers of insulating material, etc., are formed to very precisely controlled dimensions. Such dimensions are sometimes referred to as the critical dimension (CD) of the feature. It is very important in modern semiconductor processing that features be formed as accurately as possible due to the reduced size of those features in such modem devices. For example, gate electrodes may now be patterned to a width 12 that is approximately 0.2 xcexcm (2000 xc3x85), and further reductions are planned in the future. As stated previously, the width 12 of the gate electrode 14 corresponds approximately to the channel length 13 of the transistor 10 when it is operational. Thus, even slight variations in the actual dimension of the feature as fabricated may adversely affect device performance. Thus, there is a great desire for a method that may be used to accurately, reliably and repeatedly form features to their desired critical dimension, i.e., to form the gate electrode 14 to its desired critical dimension 12.
Photolithography is a process typically employed in semiconductor manufacturing. Photolithography generally involves forming a patterned layer of photoresist above one or more layers of material that are desired to be patterned and using the patterned photoresist layer as a mask in subsequent etching processes. In general, in photolithography operations, the pattern desired to be formed in the underlying layer or layers of material is initially formed on a reticle. Thereafter, using an appropriate stepper tool and known photolithographic techniques, the image on the reticle is transferred to the layer of photoresist. Then, the layer of photoresist is developed so as to leave in place a patterned layer of photoresist substantially corresponding to the pattern on the reticle. This patterned layer of photoresist is then used as a mask in subsequent etching processes, wet or dry, performed on the underlying layer or layers of material, e.g., a layer of polysilicon, metal or insulating material, to transfer the desired pattern to the underlying layer. The patterned layer of photoresist is comprised of a plurality of features, e.g., line-type features or opening-type features, that are to be replicated in an underlying process layer. The features in the patterned layer of photoresist also have a critical dimension, sometimes referred to as a develop inspect critical dimension (DICD).
In general, the stepper exposure process is performed on a stack comprised of one or more process layers or films and a layer of photoresist. For example, such a stack may be comprised of a layer of polysilicon (formed above a substrate), an anti-reflective coating (ARC) layer, and a layer of photoresist. Alternatively, the ARC layer may be omitted and the stack may be comprised of a layer of polysilicon and a layer of photoresist material. Of course, there are a vast variety of combinations of process layers and materials that may be used to form such film stacks.
Optical characteristics of the stack of process layers to be subjected to the exposure process is very important if the exposure process is to result in a patterned layer of photoresist having the desired DICD dimensions. For example, optical characteristics such as the index of refraction (xe2x80x9cnxe2x80x9d)and the dielectric constant (xe2x80x9ckxe2x80x9d) of the combined stack of materials at a particular exposure wavelength, e.g., 248 nm, may impact the ability of the stepper process to produce features in the layer of photoresist of the desired size. More particularly, variations in these optical characteristics can cause control problems in modern manufacturing operations with its inherently low tolerance for process variations due to the very small absolute size of the features to be formed. For example, the thickness of the various layers comprising the film stack to be patterned may adversely impact the optical characteristics of not only the particular process layer, but also the optical properties of the complete stack. Variations in the base materials of one or more of the films that comprise the film stack may also lead to variations in the optical characteristics of the film stack. For example, when a batch of photoresist material is replaced, it may not have the same optical characteristics as that of the previous batch of photoresist material.
All of the variations may tend to cause the DICD of features formed in the patterned layer of photoresist to be less or greater than desired. In turn, this may lead to excessive rework of the patterned layer of photoresist, i.e., the incorrectly formed layer of photoresist may have to be removed, and the process may have to be repeated. Even worse, if undetected, the variations in the patterned layer of photoresist resulting from the variations in the optical properties of the film stack, may ultimately lead to the formation of features, e.g., gate electrodes, having dimensions that are not acceptable for the particular integrated circuit device under construction. For example, transistors may be produced with gate electrodes that are too wide (relative to a pre-established target value), thereby producing transistor devices that operate at less than desirable switching speeds. All of these problems result in delays, waste, excessive costs and cause reduced yields of the manufacturing operations.
The present invention is directed to a method and system that may solve, or at least reduce, some or all of the aforementioned problems.
The present invention is generally directed to a method of controlling stepper process parameters based upon optical properties of incoming process layers, and a system for accomplishing same. In one illustrative embodiment, the method comprises forming a film stack comprised of at least one process layer and a layer of photoresist above a semiconducting substrate, illuminating the film stack, and measuring light reflected off the film stack to generate an optical characteristic trace for the film stack. The method further comprises comparing the generated optical characteristic trace to a target optical characteristic trace, and determining, based upon the comparison between the generated optical characteristic trace and the target optical characteristic trace, at least one parameter of an exposure process to be performed on the film stack. In a further embodiment, the method comprises modifying, based upon a deviation between the generated optical characteristic trace and the target optical characteristic trace, at least one parameter of an exposure process to be performed on the film stack. The film stack may be comprised of one or more process layers and the layer of photoresist.
In another illustrative embodiment, the method comprises forming a film stack comprised of at least one process layer and a layer of photoresist above a semiconducting substrate, illuminating the film stack, and measuring light reflected off the film stack to generate an optical characteristic trace for the film stack. The method further comprises correlating the generated optical characteristic trace to a calculated optical characteristic trace, the calculated optical characteristic trace having associated optical characteristics, and determining, based upon the comparison between the generated optical characteristic trace and the calculated optical characteristic trace, at least one parameter of an exposure process to be performed on the film stack. In a further embodiment, the method comprises modifying, based upon a deviation between the generated optical characteristic trace and the calculated optical characteristic trace, at least one parameter of an exposure process to be performed on the film stack. In a more specific embodiment, a library comprised of a plurality of calculated optical characteristic traces is provided, each of which correspond to a unique film stack combination.